Many modern integrated circuits utilize the detection of transitions at their input terminals to initiate an operating cycle. One type of integrated circuit that especially benefits from this technique are static memories, including both static random-access memories (SRAMs) and also read-only memories (ROMs) of both the programmable and mask-programmed variety. As is known in the art, such memories may either be implemented as stand-alone integrated circuit memory chips, or embedded within microprocessor or other VLSI or ULSI logic devices. These conventional static memories are generally operated in an asynchronous fashion, with memory access initiated upon receipt of an address value and an enable signal, and without requiring a clock signal to be presented thereto. While many static memories are "fully" static, in that peripheral circuitry such as address decoders, sense amplifiers, and input/output circuitry are maintained as fully operational, modern static memories now utilize internal dynamic clocking for low power and fast access operation. Since these internally clocked static memories do not receive an external clock signal from which internal clock signals may be generated, the technique of edge transition detection (ETD) is useful in producing a timing pulse from which the internal clock signals can be generated. Examples of memories including ETD (also referred to as "address transition detection" or "ATD") are described in Okuyama et al., "A 7.5-ns 32K.times.8 CMOS SRAM," IEEE J. Solid State Circuits, Vol. 23, No. 5 (October 1988), pp. 1054-1059, Kohno et al., "A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization," IEEE J. Solid State Circuits, Vol. 23, No. 5 (October 1988), pp. 1060-1066, and Williams et al., "An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation", IEEE J Solid State Circuits, Vol. 23, No. 5 (October 1988), pp. 1085-1094, all incorporated herein by this reference. An example of the use of ETD in input buffers, and an example of an ETD circuit, are described in my U.S. Pat. No. 5,124,584, assigned to SGS-Thomson Microelectronics, Inc., and also incorporated herein by this reference.
Those in the art will appreciate that the generation of internal clock signals from edge transition detection makes the ETD pulse a critical timing parameter in static memories. On one hand, the ETD pulse must remain active long enough to be communicated to clocked circuits distributed around the chip, so as to successfully accomplish precharge and equilibration functions. On the other hand, the duration of the ETD pulse should not be maintained so long as to delay access.
Referring now to FIG. 1, an exemplary conventional integrated circuit memory chip 1 is illustrated in plan view, showing an example of the layout location of input pads 2 and their edge transition detection (ETD) circuits 4. As is known in the art, the number of inputs that are to be monitored for edge transition can be substantial in modern SRAMs, as high as fifty or greater in modern memories (i.e., twenty or more addresses, thirty-two or more data input terminals, and associated control signal inputs). The number of such input pads 2 and ETD circuits 4 shown in FIG. 1 is much reduced from this, for purposes of clarity of description. In addition, pads other than input pads 2 are also present in integrated circuit 1 that will either not be subject to transition (e.g., power supply and ground pads) or are not to be monitored for this purpose (e.g., dedicated output pads).
According to this example, each input pad 2 is associated with an ETD circuit 4, which detects transitions at input pad 2 and generates a pulsed signal responsive thereto. Conventionally, as shown in FIG. 1, ETD circuits 4 are located on the chip near their associated input pad 2. Since the integrated circuit generates its internal clock signals for a memory cycle responsive to the detection of a transition at any one of the input pads 2, the output of each ETD circuit 4 is bussed to a summing circuit 6 (schematically illustrated as an OR function in FIG. 1), which generates a signal ETD, from which the internal clock signals for an operating cycle of circuit 1 may be generated. Alternatively, some or all of the outputs of ETD circuits 4 may be combined in a wired-OR arrangement.
Referring now to FIG. 2a, ETD circuit 4.sub.i associated with an input pad 2.sub.i and according to a conventional design is illustrated and will now be described; of course, other types and designs of ETD circuits are also used in conventional circuit 1. The signal at input pad 2.sub.i, after buffering by inverting input buffer 3.sub.i, is communicated to ETD circuit 4.sub.i as well as to the remainder of integrated circuit 1 (at node IN.sub.i), As described in the above-incorporated U.S. Pat. No. 5,124,584, ETD circuit 4 includes two legs 8a, 8b, each leg terminating at a corresponding NAND gate 12a, 12b. The outputs of NAND gates 12a and 12b are connected to inputs of NAND gate 10, the output of which drives line ETD.sub.i. Line ETD.sub.i is communicated to summing circuit 6 as shown in FIG. 1. In addition, as described in the above-incorporated U.S. Pat. No. 5,124,584, line ETD.sub.i may be used to control the latching of the input signal on node IN.sub.i for protection against spurious input pulses.
First leg 8a and second leg 8b of ETD circuit 4.sub.i each include a series of delay stages 14 implemented in the form of AND functions; for example, as shown in FIG. 2b, each of delay stages 14 may be implemented as NAND gate 14a with its inputs connected to one another, followed by inverter 14b. In first leg 8a, node IN.sub.i is connected directly to one input of NAND gate 12a, and to both inputs of the first delay stage 14 in first leg 8a; the second input of NAND gate 12a receives the inverted output from the last delay stage 14 in first leg 8a. Similarly, in second leg 8b, the inverted state of node IN.sub.i is presented to a first input of NAND gate 12b and to both inputs of the first delay stage in leg 8b; the other input of NAND gate 12b receives the inverted output of the last delay stage 14 in second leg. As such, first and second legs 8a, 8b are substantially identical, except that complementary states are provided to their inputs.
In operation, ETD circuit 4.sub.i generates a high logic level pulse at the output of NAND gate 10, at line ETD.sub.i responsive to the receipt of a logic transition at input pad 2.sub.i. For example, if input pad 2.sub.i is initially high and node IN.sub.i is initially low, the output of NAND gates 12a and 12b will both be high, causing a low logic level to be driven by NAND gate 10 at line ETD.sub.i. Upon a high-to-low transition at input pad 2.sub.i resulting in a low-to-high transition of node IN.sub.i, a high level is presented to one input of NAND gate 12a (the other input already having a high logic level thereat), causing NAND gate 12a to change state and present a low logic level to NAND gate 10 in combination with the high level previously driven by NAND gate 12b (which does not change due to this transition). This causes line ETD.sub.i to go to a high logic level until such time as the high level at node IN.sub.i propagates through delay stages 14 in first leg 8a to the second input of NAND gate 12a (as a low logic level), causing the output of NAND gate 12a to return high to force a low logic level at node ETD.sub.i. Second leg 8b operates in a similar fashion to generate the pulse at line ETD.sub.i responsive to a low-to-high transition at pad 2.sub.i.
As a result of the construction of ETD circuit 4.sub.i, the duration of the pulse at line ETD.sub.i is determined by the delay period through the delay stages 14 in first and second legs 8a, 8b (depending upon the polarity of the input transition), and thus by the number of delay stages 14 in each of first and second legs 8a, 8b. For example, FIG. 2c illustrates the construction of ETD circuit 4.sub.D, in which the first and second legs 8a, 8b, respectively, have only two delay stages 14. As a result, the width of the pulse produced by ETD circuit 4.sub.D at line ETD.sub.D, responsive to a transition at input node IN.sub.D, is shorter than that produced at line ETD.sub.i of FIG. 2a. By way of further background, ETD circuit 4.sub.D conventionally is used in connection with data input transition detection, in contrast with ETD circuit 4.sub.i being conventionally used in connection with address input transition detection.
As noted above, the duration of the edge transition detection pulse is a critical parameter in modern integrated circuits. However, in many high-speed integrated circuit designs, the design and selection of the proper ETD pulse width cannot be optimized until actual circuits are built and functionally tested under all voltage and temperature conditions. Specifically, it has been found in some first-revision circuits that the ETD pulse may be too short in some conditions, necessitating a design change to lengthen the ETD pulse. As is evident from FIGS. 2a and 2c, lengthening of the ETD pulse would be effected by the adding more delay stages 14 into each of the first and second legs 8a, 8b of each of the ETD circuits 4.sub.i, 4.sub.D in integrated circuit 1. The provision of additional delay stages into each of the ETD circuits 4.sub.i, 4.sub.D is quite inefficient from a layout standpoint, given that the additional elements must be provided for each one of the ETD circuits 4.sub.i, 4.sub.D. Furthermore, layout constraints may actually prevent the addition of delay stages 14, as has been particularly observed for input data ETD circuits 4.sub.D at those locations that lack the chip surface area for additional gates, for example as due to the space required for output buffer and driver circuitry thereat. In addition, the characterization of the effects of varying ETD pulse durations, using conventional techniques such as focused ion beam or special test modes, is made cumbersome by the multiple placements of ETD circuits 4.
It is therefore an object of the present invention to provide an edge transition detection circuit that provides efficient optimization of the duration of the edge transition detection pulse.
It is a further object of the present invention to provide such a circuit with centralized delay stage placement, thus achieving improvements in chip layout efficiency.
It is a further object of the present invention to provide such a circuit which enables individual ETD circuits associated with inputs to be implemented in minimal chip area.
It is a further object of the present invention to provide delay stages that allow for lengthening of the pulse duration by more than 100% of the input pulse duration.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.